1. Field of the Invention
The present invention relates to a placement and routing method for clock distribution circuits, a clock distribution circuit manufacturing method, a semiconductor device manufacturing method, a clock distribution circuit and a semiconductor device, and particularly to an improvement for precisely and easily adjusting the clock skew.
2. Description of the Background Art
In an LSI (Large-Scale Integrated Circuit), it is not easy to supply a clock at the same time to all sequential elements (e.g. flip-flops) included in the circuitry without causing time differences in arrival of the clock among the sequential elements receiving it. These time differences are called clock skew. Particularly, operating LSIs at high speed requires highly precise clock skew control in order to reduce the clock skew to a very small value.
Factors contributing to the clock skew include non-uniformity of positions of the sequential elements and non-uniformity of the interconnection capacitances due to differences in interconnection length among adjacent interconnections or differences in intersection ratio among inter-layer interconnections. Therefore, in order to design a clock distribution circuit with a small clock skew, it is desirable to first conduct the placement and routing of the circuitry which is supplied with the clock (the circuitry is referred to as load circuit in this specification) and then design the clock distribution circuit. However, since the clock distribution circuit is distributed over the entire area of the semiconductor chip, there is a basic contradiction that the placement and routing cannot be finally settled until the clock distribution circuit has been designed.
Known conventional layout design methods for clock distribution circuit include the technique described in Japanese Patent Application Laid-Open No. 9-269847 (1997). In this conventional technique, two or more driver elements having different characteristics are placed in each of the positions of the driver elements in the clock distribution circuit and the clock skew is controlled by selecting one of the two or the more.
FIG. 10 is a circuit diagram showing the structure of a clock distribution circuit before the clock skew has been adjusted by this conventional technique. In this clock distribution circuit, the input clock CLK is distributed through the predriver circuit 1 having cascade-connected driver elements 4a, 4b and 4c to the main driver circuit 2 having driver elements 4d to 4i. The main driver circuit 2 supplies the clock to the load circuit 3 having sequential elements 7a to 7g and clock interconnections connecting the main driver circuit 2 and the sequential elements 7a to 7g. The predriver circuit 1 in the first stage and the main driver circuit 2 in the final stage are cascade-connected.
FIG. 11 is a circuit diagram showing the structure of the clock distribution circuit obtained after the clock skew adjustment. In the example shown in FIG. 11, in order to adjust the clock skew, the driver elements 4d and 4e belonging to the main driver circuit 2 have been replaced by driver elements 5a and 5b having a larger driving capability and a larger input capacitance and the driver elements 4g and 4h have been replaced by driver elements 6a and 6b having a smaller driving capability and a smaller input capacitance.
FIG. 12 is a flowchart showing the procedure of placement and routing method for the above-described clock distribution circuit according to the conventional technique. In this method, the clock distribution circuit is designed first (S1) and the placement and routing of the entire chip including the clock distribution circuit follows (S2). In the step S2, the placement and routing of the clock distribution circuit is a temporary one. Next, the clock skew value is calculated (S3) and then whether the calculated clock skew exceeds a target value is checked (S4).
If the step S4 decides that the clock skew exceeds the target value, some of the driver elements are replaced with other driver elements having different driving capabilities and different input capacitances to adjust the clock skew (S5). Then the placement and routing is corrected as required by the replacement of the driver elements (S6) and then whether the clock skew exceeds the target value is checked again (S3, S4). The process ends if the step S4 shows that the clock skew has become equal to or smaller than the target value. In this way, the conventional technique adjusts the clock skew through replacements between driver elements having different driving capabilities and different input capacitances.
In the conventional technique, since a driver element is replaced by another driver element having a different input capacitance, the circuit characteristic varies seen from the preceding circuit. As a result, the replacement of the driver elements may require correction of the preceding circuit. Furthermore, the driver elements are generally exchanged between elements having their input pins and output pins laid out in different positions, so that replacing the driver elements requires correction of the interconnections. Thus, the placement and routing may have to be largely corrected every time a driver element is replaced, which increases the time required for the design. Moreover, correcting the placement and routing changes factors contributing to the clock skew, which makes it difficult to precisely adjust the clock skew.
The present invention has been made to solve the above-described problems of the conventional technique, and an object of the present invention is to obtain a placement and routing method for a clock distribution circuit, a clock distribution circuit manufacturing method, a semiconductor device manufacturing method, a clock distribution circuit and a semiconductor device which allow the clock skew to be adjusted highly precisely and easily.
A first aspect of the present invention is directed to a placement and routing method for a clock distribution circuit which receives a clock and supplies the clock to a load circuit. According to the first aspect, the method comprises the steps of: (a) temporarily placing and routing a group of elements having a common input capacitance to form the clock distribution circuit; and (b) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of an element belonging to the group of elements among a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin and a capacitance element interposed between an input pin and a stable potential line.
Preferably, according to a second aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the group of elements between a first driver element and a second driver element identical to the first driver element and having an opened output pin until the evaluated value of clock skew becomes equal to or smaller than the target value.
Preferably, according to a third aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the element group between a driver element and a capacitance element sharing a common input capacitance with the driver element and interposed between an input pin and a stable potential line until the evaluated value of clock skew becomes equal to or smaller than the target value.
Preferably, according to a fourth aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the element group among a plurality of driver elements having different driving capabilities and a common input capacitance and having their input pins placed in equivalent positions and their output pins placed in equivalent positions until the evaluated value of clock skew becomes equal to or smaller than the target value.
A fifth aspect is directed to a placement and routing method for a clock distribution circuit which receives a clock and supplies the clock to a load circuit. According to the fifth aspect, the method comprises the steps of: (a) temporarily placing and routing a group of driver elements having their input pins placed in equivalent positions and their output pins placed in equivalent positions to form the clock distribution circuit; and (b) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of a driver element belonging to the group of driver elements among a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and output pins placed in equivalent positions.
A sixth aspect is directed to a method of manufacturing a clock distribution circuit which receives a clock and supplies the clock to a load circuit. According to the sixth aspect, the clock distribution circuit manufacturing method comprises the steps of: (A) performing a placement and routing of the clock distribution circuit comprising the steps of (A-1) temporarily placing and routing a group of elements having a common input capacitance to form the clock distribution circuit, and (A-2) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of an element belonging to the group of elements among a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin and a capacitance element interposed between an input pin and a stable potential line; and (B) fabricating the clock distribution circuit obtained through the step of placement and routing in a semiconductor substrate.
Also, a method of manufacturing a clock distribution circuit which receives a clock and supplies the clock to a load circuit comprises the steps of: (A) performing a placement and routing of the clock distribution circuit comprising the steps of (A-1) temporarily placing and routing a group of driver elements having their input pins placed in equivalent positions and their output pins placed in equivalent positions to form the clock distribution circuit, and (A-2) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of a driver element belonging to the group of driver elements among a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions; and (B) fabricating the clock distribution circuit obtained through the step of placement and routing in a semiconductor substrate.
According to a seventh aspect, a method of manufacturing a semiconductor device comprises the steps of: (A) performing a placement and routing of a clock distribution circuit which receives a clock and supplies the clock to a load circuit comprising the steps of (A-1) temporarily placing and routing a group of elements having a common input capacitance to form the clock distribution circuit, and (A-2) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of an element belonging to the group of elements among a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin and a capacitance element interposed between an input pin and a stable potential line; and (B) fabricating, in a semiconductor substrate, the clock distribution circuit obtained through the step of placement and routing and the load circuit which is supplied with the clock from the clock distribution circuit.
Also, a method of manufacturing a semiconductor device comprises the steps of: (A) performing a placement and routing of a clock distribution circuit which receives a clock and supplies the clock to a load circuit comprising the steps of (A-1) temporarily placing and routing a group of driver elements having their input pins placed in equivalent positions and their output pins placed in equivalent positions to form the clock distribution circuit, and (A-2) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of a driver element belonging to the group of driver elements among a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions; and (B) fabricating, in a semiconductor substrate, the clock distribution circuit obtained through the step of placement and routing and the load circuit which is supplied with the clock from the clock distribution circuit.
According to an eighth aspect, a clock distribution circuit which receives a clock and supplies the clock to a load circuit comprises a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin and a capacitance element interposed between an input pin and a stable potential line.
Preferably, according to a ninth aspect, in the clock distribution circuit, the plurality of elements comprise a first driver element and a second driver element identical to the first driver element and having an opened output pin.
Preferably, according to a tenth aspect, in the clock distribution circuit, the plurality of elements comprise a driver element and a capacitance element sharing a common input capacitance with said driver element and interposed between an input pin and a stable potential line.
Preferably, according to an eleventh aspect, in the clock distribution circuit, the plurality of elements comprise a plurality of driver elements having different driving capabilities and a common input capacitance and having their input pins placed in equivalent positions and their output pins placed in equivalent positions.
According to a twelfth aspect, a clock distribution circuit which receives a clock and supplies the clock to a load circuit comprises a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions.
According to a thirteenth aspect, a semiconductor device comprises: (A) a clock distribution circuit which receives a clock, the clock distribution circuit comprising a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin, and a capacitance element interposed between an input pin and a stable potential line; and (B) a load circuit which is supplied with the clock from the clock distribution circuit.
Also, a semiconductor device comprises: (A) a clock distribution circuit which receives a clock, the clock distribution circuit comprising a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions; and (B) a load circuit which is supplied with the clock from the clock distribution circuit.
According to the method of the first aspect, the clock skew is adjusted through a replacement among elements having different driving capabilities and a common input capacitance. Accordingly the replacement of elements does not affect the preceding circuit and the clock skew can be adjusted easily and precisely.
According to the method of the second aspect, the clock skew is adjusted through a replacement between a first driver element and a second driver element identical to the first driver element and having an opened output pin, in other words, by selectively disconnecting or connecting the interconnection connected to the output pin of the driver element. Accordingly there is little need to change the placement and routing and the clock skew can be adjusted easily in a short time.
According to the method of the third aspect, the clock skew is adjusted through a replacement between a driver element and a capacitance element having a common input capacitance. Accordingly there is little need to change the placement and routing and the clock skew can be easily adjusted in a short time. Furthermore, using a capacitance element free from short-circuit current as an element not contributing to the transfer of clock reduces the current dissipation.
According to the method of the fourth aspect, the clock skew is adjusted through a replacement among a plurality of driver elements having different driving capabilities and a common input capacitance and having their input pins placed in equivalent positions and their output pins placed in equivalent positions. Accordingly there is little need for changing the placement and routing and the clock skew can be easily and more precisely adjusted in a shorter time. Further, this method can be applied to a wide range of clock distribution circuits including those of the clock tree type.
According to the method of the fifth aspect, the clock skew is adjusted through a replacement among a plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions. Accordingly there is little need for changing the placement and routing and the clock skew can be easily adjusted in a shorter time. Further, this method can be applied to a wide range of clock distribution circuits including those of the clock tree type.
According to the method of the sixth aspect, a clock distribution circuit is manufactured by fabricating a clock distribution circuit obtained through the placement and routing of the invention in a semiconductor substrate. A clock distribution circuit with precisely adjusted clock skew can thus be obtained.
According to the method of the seventh aspect, a semiconductor device is manufactured by fabricating, in a semiconductor substrate, a clock distribution circuit obtained through the placement and routing of the invention and a load circuit supplied with a clock from it. A semiconductor device with precisely adjusted clock skew can thus be obtained.
A plurality of elements having different driving capabilities and a common input capacitance are mixed in the device of the eighth aspect. This can realize precisely adjusted clock skew.
A first driver element and a second driver element identical to the first driver element and having an opened output pin are mixed in the device of the ninth aspect. This can realize precisely adjusted clock skew with a simple structure.
A driver element and a capacitance element having a common input capacitance are mixed in the device of the tenth aspect. This can realize precisely adjusted clock skew with a simple structure.
A plurality of driver elements having different driving capabilities and a common input capacitance and having their input pins placed in equivalent positions and their output pins placed in equivalent positions are mixed in the device of the eleventh aspect. This can realize more precisely adjusted clock skew.
A plurality of driver elements having different driving capabilities and having their input pins placed in equivalent positions and their output pins placed in equivalent positions are mixed in the device of the twelfth aspect. This can realize precisely adjusted clock skew.
The device of the thirteenth aspect has a clock distribution circuit of the invention and a load circuit which is supplied with a clock from it. This can realize a semiconductor device with precisely adjusted clock skew.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.